Design of a Costas loop down converter
Mike Roddewig, Seyed A. Reza Zekavat, Saeid Nooshabadi · 2009
This paper presents the the design of a digital down converter (DDC) using a digital Costas loop in a field programmable gate array (FPGA). To reduce the power dissipation we use the CIC filter to perform an efficient decimation, and then follow it with a finite impulse response (FIR) compensation filter that runs at a reduced sampling rate. The final results and performance measures are quantified and discussed. The BER performance of the Costas loop on both floating and fixed point implementations are identical.