Flexible core generation for neural signal processing
M. Diepenhorst, H. Ter Haseborg, R.S. Venema, Jos A. G. Nijhuis, Lambert Spaanenburg · 2002
The architecture and design of a CMOS core module for neural signal processing is presented. A logarithmic number representation is exploited to allow for multiplication with adaptive accuracy. This creates the facility to exchange accuracy for speed, both for the single instruction execution as during the parallelisation of a number of instructions. The core module is generated from a process independent silicon assembler. Details are given on a specific pipelined sign-magnitude implementation.