A new dc baseline stabilization scheme for neural recording microprobes
Ashwin Chandran, K. Najafi, K.D. Wise · 2003
This paper presents a novel circuit methodology for rejecting the random DC drift associated with recording microelectrodes. In this approach, a sub-threshold front end MOS transistor is used as a voltage variable resistor to clamp the large, and random DC drifts at the recording site without sacrificing AC performance. A CMOS amplifier utilizing this front-end stage (along with DC common mode feedback) has been fabricated. The amplifier measures 0.18 sq. mm and has a closed loop gain of 41 dB with a power consumption of 150 /spl mu/W. The system provides -30 dB of DC attenuation, and has a CMRR of 35 dB.