A VLSI architecture for DFT
Elizabeth Chan, S. Panchanathan · 2002
In this paper, a one-dimensional fully pipelined architecture for computing discrete-Fourier transform (DFT) is presented. It consists of an array of N basic cells (BC's) and requires N clock cycles for a N-point DFT. The architecture is modular and makes possible computation of a 2N-point transform by a simple cascade of two identical N-point transform chips. The architecture is simple and regular in structure and is hence very attractive for VLSI implementation.>