Design verification using formal techniques
Yunshan Zhu, T. Marshall · 2002
Functional verification is often the bottleneck in a hardware design flow. While simulation and coverage analysis still represent the main stream verification methodology, formal verification shows a lot of promise in its ability to exhaustively search the design space. This tutorial introduces some basic concepts for applying formal verification and presents a methodology that combines formal techniques and simulation. We use a concrete hardware design (UART) as an illustration throughout our discussion.