CrossCheck: an ASIC testability solution
C. Wirtz · 2002
A new testability solution, called CrossCheck, is examined; this solution provides a structured test methodology for many types of designs. The test structure consists of an array of test points predesigned into the base array and connected to the design. These test points allow detection of CMOS manufacturing defects modeled as open or shorted interconnects, open or shorted FETs, and shorted nodes, including all nodes within the transistor-level design. This test technology is independent of the design logic and is driven and observed by on-chip test electronics, thereby eliminating many of the design restrictions associated with other testability techniques. Common structured design-for-test techniques are reviewed and compared with CrossCheck technology. CrossCheck is specifically reviewed for its ability to handle classes of circuits that are difficult or impossible to test with the structured techniques.>