Triple Rail Logic Robustness against DPA
Victor Lomné, Thomas Ordas, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Iankowski Soares, Ney Laert Vilar Calazans · 2008
Side channel attacks are known to be efficient techniques to retrieve secret data. Within this context, the scope of this paper is to evaluate, on and for FPGA, the robustness of triple rail logic against power analyses. More precisely, this paper aims at demonstrating that the basic concepts on which leans this logic are valid and may provide interesting design guidelines to obtain DPA (Differential Power Analysis) resistant circuits.