VIPER: A 25-MHz, 100-MIPS peak VLIW microprocessor
J. Gray, A. Naylor, Arthur Abnous, Nader Bagherzadeh · 2002
The design and implementation of a very long instruction word (VLIW) microprocessor are described. The VIPER (VLIW integer processor) contains four pipelined functional units and can achieve 100 MIPS peak performance at 25 MHz. The processor is capable of performing multiway branch operations, two load/store operations, and up to four ALU (arithmetic and logic unit) operations in each clock cycle, with full register file access to each functional unit. The processor is integrated with an instruction cache controller and a data cache, requiring 450,000 transistors and a die size of 12.9 by 9.1 mm in a 1.2 /spl mu/m technology. The small, simple control paths are a distinct advantage over the significantly more complex control found in superscalar architectures due to run-time scheduling hardware.