Boundary scan with parallel test access mechanism
Ke Han, Deng Zhongliang, Jianming Huang · 2009
Along with the more complicated integrated circuit and emergence of IP based systems on a chip (SoC), new challenges are encountered in the designing for testability (DFT). The test power dissipation is one of the critical factors which should be considered carefully when designing the SoC for testability. In this paper, a parallel test access mechanism using boundary scan technique is proposed with its test controller. The test action mechanism (TAM) and the controller can be selected flexible for the test cost and the power dissipation.