A SIMD-systolic architecture and VLSI chip for the two-dimensional DCT and IDCT
Chen-Mie Wu, Alex Chiou · IEEE Transactions on Consumer Electronics · 1993
The authors present a SIMD-systolic architecture for computing the two-dimensional discrete cosine transform (2D-DCT) and inverse discrete cosine transform (2D-IDCT). With four processing elements and a dynamic switching network, this architecture can compute 2D-DCT or 2D-IDCT for 8*8 blocks in sixty-four internal clock cycles (or 128 I/O clock cycles). Currently, based on a 0.8 mu m SPDM CMOS technology, a forty-pin VLSI chip has been designed and fabricated for such an architecture. Testing results have shown that the chip is functionally correct and can compute 2D-DCT or 2D-IDCT for 8*8 blocks in 8.2 mu s.>