A new buses scheme for fast inner-product computation
R. Lin, Stephan Olariu · 2002
In this paper we adopt and modify the shift switching mechanism to propose a novel VLSI inner product processor architecture involving broadcasting on short buses, i.e. buses with no more than 8 switches each. The computation of the inner product of two positive vectors of N item each consisting of m bits takes only [log/sub 3/ (mN/7)]+1 broadcasts, plus a carry-save and a carry-propagate additions.>