Design of a real time digital beamformer for a 50MHz annular array ultrasound transducer
Pei‐Jie Cao, Koping Kirk Shung, Neel V. Karkhanis, Wo-Hsing Chen · 2003
A Field Programmable Gate Array (FPGA) based real time beamformer was developed for a six-ring annular array ultrasound transducer. Six analog to digital converters (AD9054, Analog Devices Inc.) were used to digitized the echoes at 200MHz. A Xilinx Virtex E FPGA chip which works at a 200MHz clock was used to delay the digitized echoes for beamforming. The delay for each channel was accomplished in two steps. A programmable FIFO was used for the delays of integer multiples of the clock period, a 4-tap Fractional Delay (FD) FIR filter was used for the delays less than one clock period. A high speed Cypress FIFO was used to transfer the summed beam to a DSP microprocessor (ADSP21065L). The DSP microprocessor completes envelope detection, imaging processing and transfers the image data to a computer for display through a PCI bus I/O card (PCI6534, National Instruments). The source codes for FPGA were written in VHDL language and schematic capture. A lookup table method based multiplier was designed to improve the speed of algorithm. The whole beamformer was designed in a pipeline structure; it is capable of working at 240MHz clock frequency after implemented in ISE Foundation 4.2i (Xilinx Inc). Using a Gaussian modulated sinusoidal pulse, with a 50MHz center frequency and a 50% bandwidth, the Matlab simulation study shows that the FD filter gave a maximal error of 11.2% in amplitude from the ideal waveform, and a 0.3% maximum mean square error when the required delay was 0.2 of the clock period.