Understanding yield losses in logic circuits
Davide Appello, A. Fudoli, K. Giarda, Vincenzo Tancorre, Emil Gizdarski, B. Mathew · IEEE Design & Test of Computers · 2004
Yield improvement requires understanding failures and identifying potential sources of yield loss. We focus on diagnosing random logic circuits and classifying faults. We introduce an interesting scan-based diagnosis flow, which leverages the ATPG patterns originally generated for fault coverage. This flow shows an adequate link between the design automation tools and the testers and correlation between the ATPG patterns and the tester failure reports.