A Memory Controller that Reduces Latency of Cached SDRAM
Seiji Miura, Satoru Akiyama · 2005
The proposed controller has two main control schemes, address-alignment control and dummy-cache control. These two schemes cooperatively control cached SDRAM to reduce its latency. Testing of the controller using benchmark programs demonstrated that latency was reduced 25% and execution time was reduced 13% compared to those of a sense-amplifier cache controller for standard SDRAM. The proposed controller requires 9.2 Kgates at a supply voltage of 1.8 V and an operating frequency of 133 MHz.