A Novel BIST Approach for Testing Input/Output Buffers in SOCs
Lei Chen, Zhiping Wen, Zhiquan Zhang, Min Wang · 2009
A novel Built-in Self-Test (BIST) approach to test the configurable Input/Output buffers in Xilinx Virtex series SOCs using Hard Macro has been proposed in this paper. The proposed approach can completely detects single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series FPGAs. Only total of 10 configurations are required to completely test the I/O buffers of Virtex devices.