Optimal ordering of analog integrated circuit tests to minimize test time
Scott D. Huss, R.S. Gyurcsik · 1991
This paper describes an algorithm that uses dynamic programming to order IC tests so that faulty circuits are detected early in the test sequence and the average test time is minimized.An accurate estimate of the probabilities of individual tests failing, and the joint probabilities of several tests failing is required.These probabilities can be estimated using statistical simulation techniquesor from actual circuits.The ordering algorithm is 0( Tnn2") where n is the number of tests to be ordered, and m is the number of data points.