VHDL & Verilog compared & contrasted---plus modeled example written in VHDL, Verilog and C
Douglas J. Smith · 1996
This tutorial is in two parts.The first part takes an unbiased view of VHDL and Verilog by comparing their similarities and contrasting their diffrences.The second part contains a worked example of a model that computes the Greatest Common Divisor (GCD) of two numbers.The GCD is modeled at the algorithmic level in VHDL, Verilog and for comparison purposes, C. It is then shown modeled at the RTL in VHDL and Verilog.33rd Design Automation Conference ® Permission to make digital