IDDQ testable design of static CMOS PLAs
Masaki Hashizume, H. Hoshika, H. Yotsuyangi, T. Tamesada · 2002
A new IDDQ testable design method is proposed for static CMOS PLA circuits. A testable PLA circuit of the NOR-NOR type is designed by using this method. It is shown that all bridging faults in the NOR planes of the testable designed PLA circuit can be detected by IDDQ testing with 4 kinds of test input vectors. The test input vectors are independent of the logical functions to be realized in the PLA circuit. PLA circuits are designed by using this method so that the quiescent supply current generated when they are tested can be zero. Thus, a high resolution of IDDQ tests for the PLA circuits can be obtained by using this testable design method.