A new inter-core built-in-self-test circuit for tri-state buffers in the system-on-a-chip
T. Kishi, Mitsuyasu Ohta, T. Taniguchi, H. Kadota · 2002
A new inter-core BIST circuit for tri-state buffers, T-BIST, mainly consists of simple circuits distributed in the relevant blocks. It can give an excellent test-coverage with a little additional hardware. Its configuration is not specified by each SoC structure, so it is suitable for a general/reusable testable IP.