VLSI implementation of multiprocessor system
Jun-Woo Kang, Kee-Wook Rim · 2002
Integrating multiple processors into a chip is one of the leading technologies in computer architecture. This paper describes EMPC-96 which is an on-chip multiprocessor with shared cache architecture. Four integer units, data cache, instruction cache, dispatcher, and system interfaces are integrated into single chip. 400 MIPS is a target of the performance of this design.