A 64Gb NAND Flash Memory with 800MB/s Synchronous DDR Interface
Hwang Huh, Chun-Woo Jeon, CheolWoo Yang, JaeSeok Park, Taeheui Kwon, Tai-Kyu Kang, C. Yang, Minsu Kim, B.J. Kim, MyungJin Park, DaeIl Choi, Kangwoo Park, KyeongMin Chae, G.M. Lee, SungLae Oh, ChangMan Son, YongTae Kim, JiYoung Kwon, Jin-Woo Seo, SangHyun Sung · 2012
We have developed a 64Gb MLC NAND Flash using a sub-20 nm process technology, which realizes 800MB/s data transfer rate with DDR mode. In order to achieve 800MB/s transfer rate, we introduce slim transistors of ~3 nm-thick gate oxide and dual poly gate, in addition to conventional NAND Flash transistors. Furthermore, some new novel circuitry has been implemented, such as Split Power Page Buffer, Local Sense-Amplifier (LSA) Data In/Out Architecture, Regulated Widlar Reference Generator and Low VCC Row Decoder.