Circuit simulation of CMOS faults
W.-Y. Koe, Scott F. Midkiff · 2003
The effect of short and open faults in CMOS circuits across a wide range of resistances using circuit, rather than logic, simulation is investigated. Circuit simulation is used to predict the rising and falling propagation delays and the supply current consumption for faulty and fault-free circuits when test vectors are applied. These results indicate the suitability of proposed fault detection techniques. Results for short and open faults in an inverter chain and in a complex gate full-adder are reported.>