Test and on-line debug capabilities of IEEE Std 1149.1 in UltraSPARC/sup TM/-III microprocessor
Fatemeh Golshan · 2002
The IEEE Std 1149.1 features have been essential in system and chip debug, test and manufacturing of UltraSPARC-III product. Several key testability features were achieved by adding a suite of customized instructions and logic to the chip core and I/Os to allow test and debug when in test mode or debug during normal operations. In addition, due to the design of high speed I/Os, extra logic was added to Boundary-Scan to maintain compliancy and provide support for all test and debug features. This paper discusses the above features and their logic implementations.