Digital Boltzmann VLSI for constraint satisfaction and learning
Michael Murray, Ming-Tak Leung, Kan Boonyanit, Kong Kritayakirana, James B. Burg, Gregory J. Wolff, Tokahiro Watanabe, Edward G. Schwartz, David G. Stork, Allen M. Peterson, Sun Mlcrosystems · 2016
We built a high-speed, digital mean-field Boltzmann chip and SBus board for general problems in constraint satjsfaction and learning. Each chip has 32 neural processors and 4 weight update processors, supporting an arbitrary topology of up to 160 functional neurons. On-chip learning is at a theoretical maximum rate of 3.5 x 108 con-nection updates/sec; recall is 12000 patterns/sec for typical condi-tions. The chip's high speed is due to parallel computation of inner products, limited (but adequate) precision for weights and activa-tions (5 bits), fast clock (125 MHz), and several design insights. Digital Boltzmann VLSI for Constraint Satisfaction and Learning 897 1