Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs
F.-J. Veredas, Hans-Joerg Pfleiderer · 2006
A conversion flow from a Xilinx Virtex-II Pro FPGA to a Zelix MPGA has been presented. The Zelix MPGA has a predefined regular interconnect. Experimental investigations (Feredas et al.,2006) indicate that the FPGA interconnect has more delay than the proposed MPGA. With better timing closure, studies with the MPGA router shows that a relaxed routing is area prohibitive. Timing integrity seems to be obtainable with high security