Dynamic Vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND flash memories
Kitae Park, Myounggon Kang, Soonwook Hwang, Youngsun Song, Jaewook Lee, Han-Sung Joo, OH Hyun-Sil, Jaeho Kim, Yeong-Taek Lee, Changhyun Kim, Won-Seong Lee · 2009
In this paper, dynamic Vpass ISPP schemes and optimizing Vth of erase cells are presented for achieving high program inhibition of sub-40nm MLC NAND flash and beyond. Compared to conventional method, over 40% program failure reduction after 30k P/E cycling was achieved in the proposed scheme. By optimizing erase Vth and its distribution using ISPP-after-erase, about 2 times better Vpass window margin was obtained in 40nm-node MLC NAND test chip.