An efficient microcode compiler for application specific DSP processors
Gert Goossens, Jan M. Rabaey, Joos P. L. Vandewalle, Hillarie Man · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1990
A computer program for microcode compilation for custom digital signal processors is presented. This tool is part of the CATHEDRAL II silicon compiler. The following optimization problems are highlighted: scheduling, hardware assignment, and loop folding. Efficient techniques to solve these problems are developed. This allows for the automatic synthesis of processor architectures which simultaneously exploit pipelining and parallelism. A demonstrator design is presented.>