Analysis of a QoS-based parallel packet switch for core routers
Wenjie Li, Yiping Gong, Jia Liu · 2004
High performance switch architectures with hundreds of Gbps switching capacity are needed in the next-generation routers. In this paper, we propose and analyze a parallel packet switch, which has a 160 Gbps full-duplex switched backplane, supporting 16 ports, each operating at OC192c (10 Gbps) line rate. This switch uses parallel-processing policy and can support variable-length traffic. Based on it, we also present a simple and novel QoS guaranteed scheduling algorithm, named IPRR (inlet priority round robin). By comparing it with the noted iSLIP algorithm, we prove that IPRR can provide better QoS (quality of service) control to network traffic.