A 5.1 ns, 5000 gate, CMOS PLD with selectable frequency multiplication and in-system programmability
J. Costello, Janusz Balicki, V. Bocchino, Mansun Chan, K. Nishiwaki, B. Nouban, Nguyet-Phuong Tran, Brad Vest, M. Wong · 2002
A high density programmable logic device (PLD) specifically developed for high performance and for ease of use in production flows is presented. This device is designed on a 0.5 /spl mu/m triple layer metal process to produce a 55 kmil/sup 2/ die size and with the built-in frequency multiplier, allows system performance of up to 140 MHz to be achieved.