A single chip digital signal processor and its application to real-time speech analysis
Yoshimune Hagiwara, Yoshiko Kita, Tomohiko MIYAMOTO, Y. Toba, Hideo Hara, Takashi Akazawa · IEEE Transactions on Acoustics Speech and Signal Processing · 1983
A single chip high-performance digital signal processor (HSP) has been developed for speech, telecommunication, and other applications. The HSP uses 3 μm CMOS technology and its architecture features floating point arithmetic and pipeline structure. By adoption of floating point arithmetic, data covering a wide dynamic range (up to 32 bits) can be manipulated. The input clock frequency is 16 MHz, and the instruction cycle time is 250 ns. Efficient signal processing instructions and a large internal memory (program ROM: 512 words; data RAM: 200 words; data ROM: 128 words) make it possible to construct a compact speech analysis circuit by the LPC (PARCOR) method with two HSP's. This paper describes HSP architecture, LSI design, and a speech analysis application.