Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories
Li-Ming Denq, Yu-Tsao Hsing, Cheng‐Wen Wu · IEEE Design & Test of Computers · 2009
Many embedded memories in SoCs have wide data words, leading to a high routing penalty in the BIST circuits. This novel hybrid BIST architecture reduces this routing penalty, while allowing at-speed test and diagnosis of memory cores. The MECA system facilitates mapping the diagnostic syndrome to the memory cell's defect information. A failure bitmap viewer provides visual information for design and process diagnostics.