A multimedia-oriented embedded RISC processor with a rambus DRAM controller
Kazumasa Suzuki, M. Daito, Toshiaki Inoue, K. Naehara, Masahiro Nomura, T. Iima, T. Fukuda · European Solid-State Circuits Conference · 1998
We have developed a 0.25-µm 200-MHz embedded RISC processor for multimedia applications. This processor has a dual-issue superscaler datapath that consists of a 32-bit integer unit and a 64-bit SIMD function unit, and it achieves 2000-MOPS performance. An on-chip Concurrent Rambus DRAM (C-RDRAM) controller increases memory bandwidth to 533 Mbyte/s through the Rambus channel using interleaved transaction. The controller also reduces latency using the transaction interleaving and instruction prefetching. A 64-bit 200-MHz internal bus transmits the data between the CPU core, the C-RDRAM, and the peripherals. These high-data-rate channels increase the performance of the CPU because they eliminate a bottleneck in the data supply.