Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
Young-Chul Cho, Ganghee Lee, Ki‐Young Choi, Sungjoo Yoo, Nacer-Eddine Zergainoh · Kluwer Academic Publishers eBooks · 2005
On-chip communication design includes designing software parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware parts (on-chip communica-tackle two problemunication interfaces of processor/IP/memory, etc.). For an efficient tion network, commign space, we need fast scheduling and timing analysis. In this work, we exploration of its dess. One is to incorporate the dynamic behavior of software (interrupt processing and context switching) into on-chip communication scheduling. The other is to reduce on-chip data storage required for on-chip communication, by making different communications to share a physical communication buffer. To solve the problems, we present both integer linear programming formulation and heuristic algorithm.