A Josephson systolic array processor for multiplication/addition operations
Michitada Morisue, F.-q. Li, Minoru Tobita, S. Kaneko · IEEE Transactions on Magnetics · 1991
A novel Josephson systolic array processor to perform multiplication/addition operations is proposed. The proposed systolic array processor consists of a set of three kinds of interconnected cells in which the main circuits are made by using SQUID gates. A multiplication of 2 b*2 b is performed in the single cell at a time, and an addition of three data with two bits is simultaneously performed in an another type of cell. Furthermore, information in this system flows between cells in a pipeline fashion so that a high performance can be achieved. The principle of Josephson systolic array processor is described in detail, and the simulation results are illustrated for the multiplication/addition of (4 b*4 b+8 b). The results show that these operations can be executed in 330 ps.