Real Time Video Processing on FPGA Using on the Fly Partial Reconfiguration
Sheetal Umesh Bhandari, Shaila Subbaraman, Shashank Pujari, Rashmi Mahajan · 2009
The development of Field programmable Gate Arrays (FPGAs) had tremendous improvement in last few years. FPGA based solutions have shown significant speedups compared with software and DSP based approaches for several application domains such as signal and image processing, graph algorithms, genetic algorithms and cryptography among others. Runtime Partial reconfiguration of FPGA is an attractive feature which offers countless benefits across multiple industries. Xilinx has supported partial reconfiguration for many generations of devices. This can be taken advantage of to substitute inactive parts of a hardware systems and adapt the complete chip to a different requirement of an application. This paper describes the implementation of mean and median filters for real time video signal on Virtex-4 FPGA using Partial reconfiguration. The considerable savings in device resources, bit stream size and configuration time is observed and tabulated in this paper.