A single-chip MPEG1 audio/video decoder using macrocore and cell-base implementation
Y. Katayama, Ichiro Tamitani, A. Taniguchi, Y. Ooi · 2002
A 27 MHz, 747 kTr, single-chip MPEG1 audio and video decoder has been developed. To minimize the amount of transistors, new architectures are employed for video and system decoder design. For inverse quantization of the video decoder, a modified partial product generator based on Booth's algorithm is introduced. A 3-bit-parallel distributed arithmetic is employed to achieve 316-cycle two-dimensional inverse discrete cosine transform operations to ensure real time decoding at 27 MHz operations. A variable length decoder unit consists of dedicated function blocks and a 12-bit CPU core, where fixed length decoding and motion vector calculations are executed. The chip has been fabricated on a 125 mm/sup 2/ die using a triple-metal 0.8 /spl mu/m CMOS cell-base technology.