Parallel, memory access schemes for H.263 encoder
Jarno M. A. Tanskanen, Tero Sihvo, Jarkko T. Niittylahti, Jarmo Takala, Reiner Manfred Creutzburg · 2000
In this paper, we present new parallel memory access schemes for efficient use in H.263 video encoding with on-chip parallel processors. Since video processing has variable demand for computational power depending on optional coding modes, picture resolution, desired frame rate, compression ratio, and quality etc., we propose new flexible parallel memory access schemes in a scalable processor architecture with N=2/sup n/, (n=4,5,6) parallel processors. The necessary module assignment functions are described in detail. These parallel memory access schemes provide a solution to the increased need of memory bandwidth when the number of processors is increased.