Improving Digital IC Testing with Analog Circuits
Claude Thibeault · 2006
This paper presents a promising new scan-based test technique compatible with low cost testers, called captureless delay testing (CDT). This technique uses a modified scan-chain structure, improved with analog circuits. CDT is a top-off technique multiplying the number of delay test patterns, without increasing the pattern count stored in the tester memory. It comes at a minimum performance and area overhead, with a good potential for automation