An adaptive equalizing maximum likelihood decoding LSI for magnetic recording systems
Satoshi Tanaka, Hirotsugu Kojima, Y. Okada, F. Nakazawa, Tomofumi Hikage, H. Matsushige, Minoru Kosuge, H. Miyasaka, T. Takashi, S. Hanamura · 1993
Describes a fully digital microprogrammable signal processor chip for magnetic tape (MT) recording systems which contains an adaptive equalizer, a maximum-likelihood decoder for various codes, a clock-recovery circuit, and an analog-phase-locked loop (PLL). Microprogrammable signal-processing cores reduce the number of gates by 40% compared to conventional design and provide flexibility for various recording codes. The micrograph of the fabricated LSI is shown. The process is in 1.0- mu m CMOS. Performance is summarized, and the analog input and equalized wave forms are presented.>