The Application of BIST-Aided Scan Test for Real Chips
Hideaki Konishi, Michiaki Emori, Takahisa Hiraide · Asian Test Symposium · 2006
It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with increasing design complexity. We proposed a new method, BIST-aided scan test (BAST), to reduce test cost in 2OO3 (Hiraide). Since then, we applied this method for about 200 chips, and the result is very successful to reduce test cost with less design flow impact