Partial column FFT pipelines
S.F. Gorman, James Wills · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 1995
This paper presents the development of two efficient FFT implementation algorithms which allow for more parallelization than the standard pipeline. M=2/sup q/ radix r parallel computational elements are allocated per column of the FFT flowgraph, and the constant geometry FFT is used for uniform stages. The first method solves the interstage data shuffle problem by decomposing the perfect shuffle matrix into the product of four matrices, with a memory grouping resulting in a reduction of switching from M/sup 2/ to 2M. The second method decomposes to the perfect shuffle into the product of two matrices, and the memory is partitioned such that multiport elements may be used. All required switching is accomplished via addressing of the multiport elements requiring no external switching elements. Finally implementations are presented which allow for a varied amount of parallization by using uniform modules and merely modifying interconnect wiring.>