Gigaplane: A High Performance Bus for Large SMPs
Erik Hägersten · 2003
Consequently, numerous manufacturers have resorted to building large shared-memory systems using clusters of SMP building blocks, each with only a small number of processors on relatively low bandwidth bus, connected by a network with cache coherence implemeted using directory-based “distributed shared memory” (DSM) mechanisms. While DSM-based clusters may indeed provide sufficient aggregate bandwidth to scale to a very large number of processors, they incur rather severe penalties (for example, in software complexity, hardware complexity and remote access latencies) when applied to the number of processors that can be accomodated on a bus. Our design philosophy, therefore, was to push bus technology as far as we could and only then resort to clustering.