Thread-Parallel MPEG-4 and H. 264 Coders for System-on-Chip Multi-Processor Architectures
T.R. Jacobs, V.A. Chouliaras, David J. Mulvaney · 2006
MPEG-4 and H.264 are rapidly becoming the most popular video coding algorithms for consumer devices. However, this is achieved at the expense of a computationally intensive encoding process and associated power consumption which currently limits their full deployment in portable, cost-sensitive consumer devices. We address the severe performance issue by exploiting thread-level parallelism to share the computational load between multiple processors in a system-on-chip multi-processor configuration. This can lead to significant power savings due to the lower frequency each processor is required to run. For MPEG-4, our custom multi-processor simulator delivers a reduction of 80% to 90% in dynamic instruction count per processor, at 22 processor contexts; for H.264 the theoretical reduction is a near-linear 25 % for four processor contexts, demonstrating a highly balanced multi-threaded implementation