A Bayesian neural network chip design for speech recognition system
Jhing-Fa Wang, An-Nan Suen, Jia-Ru Lee, Chung‐Hsien Wu · 2002
The Bayesian neural network (BNN) has been widely used as speech recognition template which combines the merits of the dynamic programming (DP) and hidden Markov model (HMM) methods. However, it is computationally intensive and very costly to implement using DSP component. A single chip implementation of the BNN will drastically reduce the cost and the size of many speech recognition systems. It will also make low cost implementation of real-time speech recognition system possible. In this paper, the implementation of single BNN chip for the real-time speech recognizer is presented. Fabricated in 0.8 /spl mu/m double-metal CMOS technology, the chip contains approximately 13000 transistors which occupy a 3.1/spl times/3.2 mm/sup 2/ area and has been tested to be fully functional at IMS XL-60 tester.