SIMD MULTIPLIERS FOR ACCELERATING EMBEDDED PROCESSORS IN FPGAs
Stefania Perri, M.A. Iachino, Pasquale Corsonello · Journal of Circuits Systems and Computers · 2006
This paper describes a new efficient 32×32 Single Instruction Multiple Data (SIMD) multiplier suitable for the multimedia extension of FPGA-based processors. The proposed circuit can adapt itself to 32-, 16-, and 8-bit operands widths avoiding time and power consuming reconfiguration. When implemented in an XCV400 device, the multiplier here described reaches a running frequency of about 97 MHz with an energy dissipation of just 20 mW/MHz. Comparisons with previously proposed SIMD multipliers for FPGA-based designs demonstrate that the new circuit allows the best area-time-power trade-off to be obtained.