On Generating Compact Test Sequences for Synchronous Sequential Circuits
Irith Pomeranz, Sudhakar M. Reddy · 2015
We present a procedure to generate short test sequences for syn-chronous sequential circuits described at the gate level. Short test sequences are important in reducing test application time and memory requirements. The proposed procedure constructs a test sequence using a combination of fault-independent and fault-oriented criteria. Experimental results are presented to demon-strate its effectiveness. 1.