Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues
I. Bayraktaroglu, Jim Hunt, Daniel Watkins · Proceedings/Proceedings - International Test Conference · 2006
A low cost ATE-based cache resident test methodology is presented in this paper for testing cores of microprocessor chips with non-deterministic main memory access. No non-determinism (ND) or training sequence handling of the SerDes is needed, simplifying test development, reducing the need for expensive next generation ATE that handle SerDes, and simplifying debug as the SerDes are not tested or used. Even low cost testers (LCT) with low speed interface support initially developed for structural test can be enabled to run these tests