A multi-layer neural network architecture with external weight memory
Navid Yazdi, Majid Ahmadi, M. Shridhar · 2002
An architecture for VLSI implementation of multi-layer neural networks is presented in this paper. It is based on direct utilization of external digital weight memory. The architecture lends itself easily to a chip-in-loop training scheme which is controlled by a digital host computer. This architecture has been applied for VLSI implementation of the classifier unit of a moment-invariant contour-shape recognition system.>