A 10 Mb frame buffer memory with Z-compare and A-blend units
Kazunari Inoue, Hiroki Nakamura, H. Kawai · IEEE Journal of Solid-State Circuits · 1995
A 3-D frame buffer memory that integrates Z-compare and A-blend units onto a 10 Mb DRAM chip is presented. High I/O bandwidth and a new pixel ALU implementation greatly Improve rendering performance. The 3-D-RAM converts the fundamental rendering operation from read-modify-write into mostly-write. A triple-ported SRAM cache operating at a frequency of 100 MHz and an internal 256-b wide bus accelerate rendering operations to 400 Mpixel/s, ten times faster than conventional DRAM or VRAM. A VIDEO port is provided for CRT refresh with less than 2% area penalty by virtue of a rectangular shaped page. A quad-polysilicon, double metal, 0.5 /spl mu/m CMOS process is employed.