An O(log/sup 2/ N) parallel algorithm for output queuing
Amit Prakash, Sharoon Sharif, A. Aziz · 2003
Output queued switches are appealing because they have better latency and throughput than input queued switches. However, they are difficult to build: a direct implementation of an N/spl times/N output-queued switch requires the switching fabric and the packet memories at the outputs to run at N times the line rate. Attempts have been made to implement output queuing with slow components, e.g., by having memories at both inputs and outputs running at twice the line rate. In these approaches, even though the packet memory speed is reduced, the scheduler time complexity is high - at least /spl Omega/(N). We show that idealized output queuing can be simulated in a shared memory architecture with (3N-2) packet memories running at the line rate, using a scheduling algorithm whose time complexity is O(log/sup 2/ N) on a parallel random access machine (PRAM). The number of processing elements and memory cells used by the PRAM are a small multiple of the size of the idealized switch.